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Addendum
HC908JB8AD/D Rev. 0, 4/2002 Addendum to MC68HC908JB8 Technical Data
Freescale Semiconductor, Inc...
This addendum provides additional information to the MC68HC908JB8 Technical Data, Rev. 2 (Motorola document number MC68HC908JB8/D),
MC68HC08JB8A
The MC68HC08JB8A is the ROM part equivalent to the MC68HC908JB8. The entire MC68HC908JB8 data book apply to this ROM device, with exceptions outlined in this addendum. Table 1. Summary of MC68HC08JB8A and MC68HC908JB8 Differences
MC68HC08JB8A Memory ($DC00-$FBFF) User vectors ($FFF0-$FFFF) Registers at $FE08 and $FF09 8,192 bytes ROM 16 bytes ROM Not used; locations are reserved. $FC00-$FDFF: Not used. $FE10-$FFDF: Used for testing purposes only. VDD level (5V logic) MC68HC908JB8 8,192 bytes FLASH 16 bytes FLASH FLASH related registers. $FE08 -- FLCR $FF09 -- FLBPR Used for testing and FLASH programming/erasing. VREG level (3.3V logic)
Monitor ROM ($FC00-$FDFF and $FE10-$FFDF) OSC1 and OSC2 pins
MCU Block Diagram
Figure 1 shows the block diagram of the MC68HC08JB8A.
Memory Map
The MC68HC08JB8A has 8,192 bytes of user ROM from $DC00 to $FBFF, and 16 bytes of user ROM vectors from $FFF0 to $FFFF. On the MC68HC908JB8, these memory locations are FLASH memory. Figure 2 shows the memory map of the MC68HC08JB8A.
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INTERNAL BUS M68HC08 CPU PTA7/KBA7 (3) PTA : PTA0/KBA0 (3) ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE DDRB PTB PTB7-PTB0 (3) DDRA
HC908JB8AD/D
CPU REGISTERS
CONTROL AND STATUS REGISTERS -- 64 BYTES TIMER INTERFACE MODULE
USER ROM -- 8,192 BYTES
MONITOR ROM -- 464 BYTES LOW VOLTAGE INHIBIT MODULE DDRD PTD
USER ROM VECTORS -- 16 BYTES
DDRC
PTC
USER RAM -- 256 BYTES BREAK MODULE
PTC7-PTC0 (3)
PTD7-PTD6 (4) PTD5-PTD2 (4) (5) PTD1-PTD0 (4) (6) PTE4/D- (3) (4) (5)
(1)
OSC1 OSCILLATOR POWER-ON RESET MODULE
(1) OSC2
(1), (2)
RST
SYSTEM INTEGRATION MODULE
PTE3/D+ (3) (4) (5) DDRE PTE COMPUTER OPERATING PROPERLY MODULE PTE2/TCH1 (3) PTE1/TCH0 (3) PTE0/TCLK (3) USB MODULE
(1), (3)
IRQ
IRQ MODULE
VDD POWER
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INTERNAL VOLTAGE REGULATOR (1) Pins have 5V logic. (2) Pins have integrated pullup device. (3) Pins have software configurable pull-up device. (4) Pins are open-drain when configured as output. (5) Pins have 10mA sink capability. (6) Pins have 25mA sink capability.
VSS
VREG (3.3 V)
Shaded blocks indicate differences to MC68HC908JB8
Figure 1. MC68HC08JB8A Block Diagram
LS USB TRANSCEIVER USB ENDPOINT 0, 1, 2
Addendum to MC68HC908JB8 Technical Data
Freescale Semiconductor, Inc.
HC908JB8AD/D MC68HC08JB8A
$0000 $003F $0040 $013F $0140 $DBFF $DC00 $FBFF $FC00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FFDF $FFE0 $FFEF $FFF0 $FFFF
I/O Registers 64 Bytes RAM 256 Bytes Unimplemented 56,000 Bytes ROM 8,192 Bytes Unimplemented 512 Bytes Break Status Register (BSR) Reset Status Register (RSR) Reserved Break Flag Control Register (BFCR) Interrupt Status Register 1 (INT1) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Break Address High Register (BRKH) Break Address Low Register (BRKL) Break Status and Control Register (BRKSCR) Reserved Monitor ROM 464 Bytes Reserved 16 Bytes ROM Vectors 16 Bytes
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Figure 2. MC68HC08JB8A Memory Map
Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D
Reserved Registers
The two registers at $FE08 and $FE09 are reserved locations on the MC68HC08JB8A. On the MC68HC908JB8, these two locations are the FLASH control register and the FLASH block protect register respectively.
Monitor ROM
The monitor program (monitor ROM: $FE10-$FFDF) on the MC68HC08JB8A is for device testing only. $FC00-$FDFF are unused.
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Electrical Specifications DC Electrical Characteristics
Electrical specifications for the MC68HC908JB8 apply to the MC68HC08JB8A, except for the parameters indicated below.
Table 2. DC Electrical Characteristics
Characteristic(1) Regulator output voltage Output high voltage (ILoad = -2.0 mA) PTA0-PTA7, PTB0-PTB7, PTC0-PTC7, PTE0-PTE2 Output low voltage (ILoad = 1.6 mA) All I/O pins (ILoad = 25 mA) PTD0-PTD1 in ILDD mode (ILoad = 10 mA) PTE3-PTE4 with USB disabled Input high voltage All ports, OSC1 IRQ, RST Input low voltage All ports, OSC1 IRQ, RST Output low current (VOL = 2.0 V) PTD2-PTD5 in LDD mode VDD supply current, VDD = 5.25V, fOP = 3MHz Run, with low speed USB(3) Run, with USB suspended(3) Wait, with low speed USB(4) Wait, with USB suspended(4) Stop(5) 0 C to 70C -- -- -- -- -- 6.0 (5.0) 5.5 (4.5) 4.0 (3.0) 3.0 (2.5) 30 7.5 6.5 5.0 4.0 100 mA mA mA mA Symbol VREG VOH Min 3.0 VREG -0.8 Typ(2) 3.3 -- Max 3.6 -- Unit V V
VOL
-- -- -- 0.7 x VREG 0.7 x VDD VSS VSS 12 (17)
-- -- -- -- -- -- -- 17 (22)
0.4 0.5 0.4 VREG VDD 0.3 x VREG 0.3 x VDD 22 (27)
V
VIH
V
VIL
V
IOL
mA
IDD
A
Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D MC68HC08JB8A
Table 2. DC Electrical Characteristics
Characteristic(1) I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR re-arm voltage(6) POR rise-time ramp rate(7) Symbol IIL IIN COut CIn VPOR RPOR VDD+VHI RPU Min -- -- -- -- 0 0.035 1.4 x VDD 25 4 1.2 2.8 (2.4) 40 5 1.5 3.3 (2.7) Typ(2) -- -- -- -- -- -- Max Unit
10 1
12 8 100 -- 2 x VDD 55 6 2.0 3.8 (3.0)(8)
A A
pF mV V/ms V
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Monitor mode entry voltage Pullup resistors Port A, port B, port C, PTE0-PTE2, RST, IRQ PTE3-PTE4 (with USB module disabled) D- (with USB module enabled) LVI reset
k
VLVR
V
1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fXCLK = 6 MHz); all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; 15 k 5% termination resistors on D+ and D- pins; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD 5. STOP IDD measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 k 5% between VREG and D- pins and 15 k 5% termination resistor on D+ pin; no port pins sourcing current. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VREG is not reached before the internal POR reset is released, RST must be driven low externally until minimum VREG is reached. 8. The numbers in parenthesis are MC68HC08JB8 (non-A part) values.
Memory Characteristics Table 3. Memory Characteristics
Characteristic RAM data retention voltage Symbol VRDR Min 1.3 Max -- Unit V
Notes: Since MC68HC08JB8A is a ROM device, FLASH memory electrical characteristics do not apply.
Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D
MC68HC08JB8A Order Numbers
These part numbers are generic numbers only. To place an order, ROM code must be submitted to the ROM Processing Center (RPC). Table 4. MC68HC08JB8A Order Numbers
MC order number MC68HC08JB8AJP MC68HC08JB8AJDW MC68HC08JB8AADW Package 20-pin PDIP 20-pin SOIC 28-pin SOIC 44-pin QFP Operating temperature range 0 C to +70 C 0 C to +70 C 0 C to +70 C 0 C to +70 C
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MC68HC08JB8AFB
MC68HC08JB8A and MC68HC08JB8 Differences
The MC68HC08JB8A and MC68HC08JB8 are identical devices, except for the following: Table 5. MC68HC08JB8A and MC68HC08JB8 Differences
MC68HC08JB8A OSC1 and OSC2 pins Output low current on PTD2-PTD5 in LDD mode Operating IDD currents LVI trip points VDD level (5V logic) MC68HC08JB8 VREG level (3.3V logic)
See Table 2 . DC Electrical Characteristics. The numbers in parenthesis are MC68HC08JB8 values.
Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D NOTES
NOTES
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Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D Rev. 0 4/2003


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